1. Field of the Invention
The present invention relates to a ferroelectric memory device.
2. Description of the Related Art
Conventionally, FeRAM (Ferroelectric Random Access Memory) is well known ferroelectric memory. One example is the 2-transistor 2-capacitor/1-bit type. In FeRAM of this type, pairs of memory cells, each of which is constituted by a transistor and a capacitor, are used to store binary information sets.
FeRAM is disclosed in the following well known reference: xe2x80x9cLow Power Consumption, High-speed LSI Techniquexe2x80x9d, Realize Co., Ltd., pp. 234-240.
A memory cell array commonly used for FeRAM includes a matrix-shaped arrangement of memory cells. The structure of one column of such a memory cell array is shown in FIG. 18. As is shown in FIG. 18, for FeRAM 2000, memory cells M0, M1, . . . respectively include selection transistors T0, T1, . . . and ferroelectric capacitors C0, C1, . . . . The ferroelectric capacitors C0, C1, . . . store directionally polarized binary data.
In FeRAM of the 2-transistor 2-capacitor/1-bit type, binary data having different values are stored in the ferroelectric capacitors (e.g., the capacitors C0 and C1) of paired memory cells (e.g., the memory cells M0 and M1).
FIG. 19 is a timing chart for the data reading operation performed for FeRAM 2000. In FIG. 19, L denotes a ground potential and H denotes a power voltage Vcc. Vh denotes a potential that is higher than the power voltage Vcc the equivalent of the threshold value Vt of the selection transistors T0, T1 . . . .
First, at time t1, the potential on a precharge control line PCHG is set to L, and transistors PCT0 and PCT1 are rendered off. At this time, bit lines BL0 and BL1 are placed in the floating state.
Next, at time t2, the potentials on word lines WL0 and WL1 are set to Vh, and the selection transistors T0 and T1 are rendered on.
When at time t3 the potential on a plate line PL0 is set to H, the potential on the plate line PL0 is applied to the bit lines BL0 and BL1 via the ferroelectric capacitors C0 and C1 and the selection transistors T0 and T1, so that a read potential is generated across the bit lines BL0 and BL1. Since the capacitances of the ferroelectric capacitors C0 and C1 differ depending on the polarization direction, the values of the read potentials generated across the bit lines BL0 and BL1 also differ in accordance with the polarization direction.
At time t4, the potential of a signal SAE is set to H, and a sense amplifier SA is activated. Then, the potentials across the bit lines BL0 and BL1 are amplified.
At time t5, the potential on the plate line PL0 is returned to L, and at the same time, the potential of a column selection signal SEL is set to H. Then, bit line selection transistors SET0 and SET1 are rendered on and the read potentials on the bit lines BL0 and BL1 are output to a data bus 2210.
At time t6, the potential on the precharge control line PCHG is set to H, and the potentials on signal lines SAE and SEL are set to L. Then, the transistors PCT0 and PCT1 are rendered on to ground the bit lines BL0 and BL1 and the sense amplifier SA halts the output of read data.
Finally, at time t7, the potentials on the word lines WL0 and WL1 are set to L, and the selection transistors T0 and T1 are rendered off.
FIG. 20 is a conceptual diagram for explaining the state shifting of a ferroelectric capacitor. The horizontal axis represents a voltage V, and the vertical axis represents polarization Pr [xcexcC/cm2]. As is shown in FIG. 20, the relationship existing between the voltage V and the polarization Pr describes a hysteresis curve H, and the inclination of the hysteresis curve H corresponds to the capacitance [q/V] across the ferroelectric capacitor.
In FIG. 20, assume that the coordinates of an intersection A of the hysteresis curve H and the Pr axis (area of Pr greater than 0) are (0, p0). Further, when a linear line S1 is drawn so that it passes through point B(Vcc,p0) and intersects linear line Pr=p0 at an angle of xcex8, assume that the coordinates of an intersection C of the linear line S1 and the ascending segment of the hysteresis curve H are (v1, p1). The angle xcex8 is then determined in accordance with the capacitance on the bit line. The V coordinate v1 of the point C matches the inter-terminal voltage at the ferroelectric capacitor, and the difference Vcc-v1 between the V coordinates of the points B and C matches the potential on the bit line. Therefore, when Pr greater than 0 (the stored value is xe2x80x9c0xe2x80x9d), the potential V0 output to the bit line is represented by Vcc-v1.
Further assume in FIG. 20 that the coordinates of an intersection D of the hysteresis curve H and the Pr axis (area of Pr greater than 0) are (0, p2). Furthermore, when a linear line S2 is drawn so that it passes through point E (Vcc, p2) and intersects a linear line Pr=p2 at an angle xcex8, the coordinates of an intersection F of the linear line S1 and the ascending segment of the hysteresis curve H are (v2, p3). Also, in this case, the V coordinates v2 of the point F match the inter-terminal voltage at the ferroelectric capacitor, and the difference Vcc-v2 between the V coordinates of the points E and F matches the bit line potential. Therefore, when Pr less than 0 (the stored value is xe2x80x9c1xe2x80x9d), the potential V1 output to the bit line is represented by Vcc-v2.
As is apparent from FIG. 20, V0 less than V1 is established, and the angle xcex8 is such that the read margin xcex94V is at its maximum. In order to increase the angle xcex8, only the capacitance on the bit line need be increased.
FIG. 21 is a graph showing the relationship between the reading margin xcex94V and a ratio Cbl/Cs of the capacitance Cbl on the bit line to the capacitance Cs on the ferroelectric capacitor. As is apparent from FIG. 21, when Cbl/Cs is between 4 and 5, the maximum reading margin is obtained. Further, when the reading margin is increased, the reliability of the data read is increased and the yield provided by the FeRAM is improved.
The capacitances Cb1 on the bit lines BL0 and BL1 are the junction capacitances of the transistors T0, T1, . . . and PCT0, PCT1, . . . , which are connected to the bit lines BL0, BL1, . . . , or are the parasitic capacitances on the bit lines BL0, BL1, . . . . In most cases, the capacitances on the bit lines BL0, BL1, . . . are derived from the junction capacitances provided by the selection transistors T0, T1, . . . . For conventional FeRAMs, several hundreds of selection transistors are connected to one bit line in order to increase the capacitances Cbl placed on the bit lines BL0, BL1, . . . .
However, when the capacitances Cbl placed on the bit lines BL0, BL1, . . . are increased, this is accompanied by an increase in the power consumed by the sense amplifier SA (see FIG. 18). For data reading, the potentials on the bit lines BL0, BL1, . . . are amplified until they reach the level of the power potential Vcc or the ground potential, and this amplification to the power potential Vcc is implemented by a current supplied to the bit lines BL0, BL1, . . . by the sense amplifier SA. Therefore, as the capacitances placed on the bit lines BL0, BL1, . . . are large, the consumption of power by the sense amplifier SA is increased.
For these reasons, a demand exists for ferroelectric memory for which the read data is reliable and the consumed power is small.
According to the present invention, a ferroelectric memory device comprises:
a plurality of memory cells, arranged in the shape of a matrix, including capacitors, for which a ferroelectric substance is used, on which binary data is stored while the capacitors are in a polarized state;
a plurality of bit lines, connected to several of the memory cells aligned in a first direction;
a plurality of word lines, connected in series to the memory cells aligned in a second direction perpendicular to the first direction;
a plurality of plate lines, which correspond to the memory cells and which are electrically connected to the capacitors;
a sense amplifier for amplifying a potential applied to each of the bit lines; and
a controller for, when potentials consonant with data stored in one of the memory cells are applied to one of the bit lines, electrically connecting the memory cell that outputs the potential to a predetermined number of other memory cells via the bit line, or for, when the sense amplifier amplifies the potential applied to the bit line, reducing to less than the predetermined number the number of memory cells that are to be electrically connected via the bit line to the memory cell the source of the potential.